Cite this Article
Wang Jun, Peng Xiao-Mei, Liu Zhi-Jun, Wang Lin, Luo Zhen, Wang Dan-Dan. Observation of nonconservation characteristics of radio frequency noise mechanism of 40-nm n-MOSFET . Chinese Physics B, 2018, 27(2): 027201  
Permissions
Observation of nonconservation characteristics of radio frequency noise mechanism of 40-nm n-MOSFET
Wang Jun1, †, Peng Xiao-Mei1, Liu Zhi-Jun2, Wang Lin1, Luo Zhen1, Wang Dan-Dan1
School of Information Engineering, Southwest University of Science and Technology, Mianyang 621010, China
Department of Physics, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139, USA

 

† Corresponding author. E-mail: junwang@swust.edu.cn

Project supported by the National Natural Science Foundation of China (Grant No. 69901003) and the Scientific Research Fund of Sichuan Provincial Education Department.

Abstract

Bias non-conservation characteristics of radio-frequency noise mechanism of 40-nm n-MOSFET are observed by modeling and measuring its drain current noise. A compact model for the drain current noise of 40-nm MOSFET is proposed through the noise analysis. This model fully describes three kinds of main physical sources that determine the noise mechanism of 40-nm MOSFET, i.e., intrinsic drain current noise, thermal noise induced by the gate parasitic resistance, and coupling thermal noise induced by substrate parasitic effect. The accuracy of the proposed model is verified by noise measurements, and the intrinsic drain current noise is proved to be the suppressed shot noise, and with the decrease of the gate voltage, the suppressed degree gradually decreases until it vanishes. The most important findings of the bias non-conservative nature of noise mechanism of 40-nm n-MOSFET are as follows. (i) In the strong inversion region, the suppressed shot noise is weakly affected by the thermal noise of gate parasitic resistance. Therefore, one can empirically model the channel excess noise as being like the suppressed shot noise. (ii) In the middle inversion region, it is almost full of shot noise. (iii) In the weak inversion region, the thermal noise is strongly frequency-dependent, which is almost controlled by the capacitive coupling of substrate parasitic resistance. Measurement results over a wide temperature range demonstrate that the thermal noise of 40-nm n-MOSFET exists in a region from the weak to strong inversion, contrary to the predictions of suppressed shot noise model only suitable for the strong inversion and middle inversion region. These new findings of the noise mechanism of 40-nm n-MOSFET are very beneficial for its applications in ultra low-voltage and low-power RF, such as novel device electronic structure optimization, integrated circuit design and process technology evaluation.

PACS: 72.70.+m;72.30.+q;73.43.Fj
Keyword:nanoscale MOSFET;non-conservation characteristics;noise mechanism;radio frequency
1. Introduction

With the advent and application of metal–oxide–semiconductor field-effect transistor (MOSFET), the research and characterization of its noise mechanism has become the focus of research.Its low frequency noise is used to identify the deep level defects of the device, in order to ascertain the reliability of the device. With the development of down-scaling of technology, it is very important to understand the high frequency noise characteristics of nanoscale MOSFET. Its radio frequency (RF) noise is modeled to meet the needs of the optimal designs of various information transmission and processing systems.[1–5]

The needs of low-voltage and low-power design of modern and future wireless communication/network systems have greatly stimulated the applications of digital complementary metal–oxide–semiconductor (CMOS) technology in RF analog integrated circuits. One of the most important problems is how to establish a precise RF equivalent noise circuit model of MOFET. In the two-port equivalent noise model of the common source configuration of MOSFET shown in Fig. 1, the drain current noise (Sid) has always been a concern because it characterizes the noise mechanism of MOSFET.[1,3,6–11] The power spectral density (PSD) of induced-gate current noise (Sig), which is correlated with Sid(Sigid*), is 2–3 orders of magnitude lower in dimension than Sid.[1–7,12,13] Therefore, Sid is the dominant noise source of MOSFET, but the most important problem is that the noise mechanism for different channel lengths may be channel thermal noise or shot noise.

Fig. 1. Equivalent noise current source representation of MOSFET.

The long channel thermal noise model has been extensively studied for submicron channel MOSFET, and many different models have been proposed. A physical model based on the electronic structure of devices for a long channel MOSFET is[12] where δ is the noise parameter, k is the Boltzmann’s constant, T is the absolute temperature parameter and characterizes its thermal noise mechanism, VGT = VGS − VT is the gate overdrive voltage, VT = VT0 − VDS is the threshold voltage taking into account the drain-induced barrier lowering effect. The parameters in the bracket are the microelectronic process structure parameters of the device.

The most famous compact model for submicron and deep-submicron channel MOSFET is[1,13] where γ is the bias-dependent noise parameter and gds0 is the output conductance at zero drain voltage (VDS). The accuracy of the model from the strong inversion (SI) region to the weak inversion (WI) region has been confirmed.

Recently, no thermal noise has been observed for an ultra-short (ballistic) channel MOSFET because the scattering centers inside the channel are scarce.[1] Therefore, the shot noise characteristics of around-10-nm MOSFET are observed in the SI and middle inversion (MI) region.[6] The shot noise in ballistic MOSFET has been modeled by modifying the full shot noise model[1,7] where the drain current IDS characterizes its shot noise mechanism, the Fano factor F is used to characterize the suppressed shot noise in the SI region. The reason for this suppression has been explained by the Fermi exclusion principle at the barrier and the Coulomb interactions between the carriers already in the channel.[1] Also, F will tend to 1 at a given small drain current.[1,6–8] Recently, a theoretical model of the Fano factor in the strong inversion region has been given.[9]

A more complicated physical model of shot noise based on the device electronic structure for short channel MOSFET is[10] where vth = kT/q is the thermal voltage, n is the sub-threshold slope factor, and Voff = VT,sub − VT is the offset voltage, which can be extracted from the current–voltage characterization in the sub-threshold region.

At present, the noise investigations of short channel MOSFET focus on the SI and MI region, and the noise mechanism is verified to be the suppressed shot noise for channel length 40 nm or less,[7,9,13] but the thermal noise for channel length longer than 40 nm.[2,7] The WI region is becoming more important for low-voltage and low-power RF applications,[4,5,11,14,15] but recent studies for the devices of 40 nm,[5] 65 nm,[14] and 80 nm[15] have focused on the characterizations of the macroscopic four noise parameters independent of the noise mechanism. In addition, since the millimeter wave effects of Sig and Sigid* in sub-threshold region are very obvious; recent studies[4,5,11] have focused on their accurate and continuous modeling from SI to WI region. Unfortunately, Sig and Sigid* cannot be used to characterize the device noise mechanism. The following noise observations of 40 nm n-MOSFET are carried out for Sid because the noise mechanism of MOSFET is characterized by Sid.[1,3,6–11]

In this paper, a physic-based compact model for Sid is proposed and validated. New observations of 40-nm n-MOSFET noise controlled by gate voltage (VGS) and drain voltage (VDS) simultaneously from SI to WI region are presented. The special bias non-conservation phenomenon is also characterized by noise analysis and measurement.

2. Device and experiments

In this paper, two n-MOS transistors respectively with channel lengths of 40 nm and 120 nm, fabricated by a 40-nm COMS process, are used for the unified comparison and identification of noise mechanism. The 120-nm device is used to calibrate the noise measurement and analysis method used here because its thermal noise mechanism is well known and can accurately be predicted by the well-proved long channel thermal noise model.[1,3,4,13] Two n-MOS transistors both have M = 6 (the number of devices in parallel), Nf = 10 (the number of fingers per device) and W = 2 μm (width). The measurement frequency ranges from 1 GHz to 60 GHz where the low-frequency noise is negligible.

The RF equivalent circuit model shown in Fig. 2[2,11,16] is used to characterize the device noise behaviors. Figure 3 shows the scattering (S) parameters of 40-nm n-MOSFET in a frequency range of 1 GHz–60 GHz measured by a commercial Agilent 8510C network analyzer. Thus, the parameters of small-signal equivalent circuit of 40-nm n-MOSFET shown in Table 1 can be carefully extracted by using the dummy open and short de-embedding technique.[4,5,17,18]

Fig. 2. RF noise equivalent circuit model for tested n-MOSFET.
Fig. 3. Measured S parameters of 40-nm n-MOSFET in a frequency range of 1 GHz–60 GHz and with VDS = 1.1 V and VGS = (a) 0.18 V, (b) 0.35 V, and (c) 0.7V.
Table 1.

Extracted small-signal parameters of 40-nm n-MOSFET in Fig. 2 which can benefit the noise analysis at VDS = 1.1 V.

.

The four noise parameters for 40-nm n-MOSFET, shown in Fig. 4, can also be measured by using a commercial spread-spectrum Agilent N8976B noise figure analyzer.[17–20] After de-embedding the parasitic and noise, the measured Sid characterizing the devices noise mechanism can be obtained from[3–5,13] where

Fig. 4. (color online) Measured four noise parameters of 40-nm n-MOSFET in a frequency range of 1 GHz–60 GHz, showing plots of (a) equivalent noise resistance Rn against frequency, (b) minimum noise figure NFmin against frequency, (c) real part of optimum source admittance Gopt against frequency, (d) imaginary part of optimum source admittance Bopt against frequency.

Figure 5 shows the observation of noise mechanism for 120-nm n-MOSFET from SI to WI region. The good agreement between the extracted channel thermal noise and its theoretical value based on model (2) validates the reliabilities of noise measurement and analysis method used here.

Fig. 5. (color online) Plots of measured Sid against IDS for 120-nm n-MOSFET at 10 GHz and VDS = 1.1 V.
3. Experimental results and discussion
3.1. Noise source characterization and modeling of 40-nm n-MOSFET

Figure 6 shows that the noise predicted by full shot noise model increases monotonically with VGS.[6,13] The measurement results indicate that in the SI region, the noise mechanism of 40-nm n-MOSFET acts as the suppressed shot noise similar to the recent theoretical prediction,[7,9,13] but a weak temperature dependence is observed. In the MI region, the noise mechanism is near to full shot noise in which the measurement results are all the same as the expectations from model (3). Some own features of 40-nm n-MOSFET are observed that the drain current noise separates itself gradually from full shot noise in the WI region, and ultimately turns into the thermal noise with obvious temperature dependence. Figure 6 also shows that in the WI region, a severe underestimation of noise intensity is obtained if only the shot noise model is used consistently.

Fig. 6. Plots of measured Sid against VGS for 40-nm n-MOSFET at 10 GHz, VDS = 1.1 V, and two different temperatures.

For explaining the bias non-conservation characteristics of noise mechanism of 40-nm n-MOSFET shown in Fig. 6, some equivalent circuit parameters of device shown in Table 1 are analyzed.

Firstly, with the improvements of process technology on gate materials, the number of gate fingers and gate layout, the gate parasitic resistance Rg has been greatly reduced. However, the value of Rg in Table 1 is still much larger than those of Rd and Rs. As a common source configuration, device itself provides the transconductance gain gm from the source to the drain. Therefore, the noise contribution of Rg to Sid has always been considered seriously; its strong influence on the long channel[3,4] and 65-nm[2] n-MOSFET in SI region has been confirmed. The thermal noise contribution of Rg to Sid can be modeled by[2–4,8] Secondly, Table 1 also shows that drain to substrate parasitic capacitor Cdb and substrate parasitic resistance Rb may have a greater influence on intrinsic noise current. This is because at low frequencies, idealized substrates do not have coupling effects. However, as the operating frequency rises up to GHz, the reduction of junction capacitance leads to severe coupling between drain and substrate.[21] Such a nonideal coupling effect will obviously affect the characteristic of the output admittance by . Therefore, the noise contribution of substrate parasitic to Sid can be modeled by

If the intrinsic drain current noise is assumed to be the suppressed shot noise, its PSD can be modeled by Eq. (3). Thus, a compact RF noise model for drain current noise of 40-nm n-MOSFET can be described as

In order to evaluate the noise contributions of Rg and Rb in different operating regions and to verify model (8), the typical PSD values listed in Table 2 are calculated by using the extracted parameters shown in Table 1. Further observations for device noise mechanism are discussed as follows.

Table 2.

Typical noise contributions of Rg and Rb for Sid at room temperature (300 K) and 10 GHz. The and represent the shot noise PSDs for intrinsic drain current noise at different VDS.

.
3.2. Further observation of noise mechanism change and model verification

As shown in Fig. 7, the characteristics of suppressed (F ≈ 0.301) shot noise of 40-nm n-MOSFET in saturation region (big IDS) is confirmed by noise measurements at VGS = 0.7 V. The F ≈ 0.301 is consistent with the theoretically predicted value of 0.3 in Ref. [9], which can verify the validity of model (8) about the hypothesis of the intrinsic drain current noise mechanism. Figure 7 also shows that the noise mechanism in the saturation region looks like suppressed shot noise, but it is weakly affected by the thermal noise of Rg. In the linear region, as the VDS decreases, the suppression of the shot noise is reduced (i.e., F → 1), but when IDS is extremely small, the whole noise is almost controlled by Rg. These particular bias non-conservation properties of 40-nm n-MOSFET are also verified by comparing the noise data between 300 K and cryogenic temperature (77 K). Note that as the predictions in the column of VGS = 0.7 V in Table 2, the thermal noise in the SI region has a slight influence on the intrinsic shot noise property of the device even though the short channel process has significantly reduced Rg. This is because the transconductance amplification of common source configuration is very strong under the condition of high VDS in the SI region, i.e., very high gm, which leads to the strong thermal noise contribution of Rg modeled by Eq. (6). But Rb is very small in SI region because the conduction characteristic of channel is very good. Therefore, the model (7) shows that Rb contributes little to the substrate coupling thermal noise as predicted in the column of VGS = 0.7 V in Table 2.

Fig. 7. (color online) Plots of measured and calculated Sid against IDS for 40-nm n-MOSFET at VGS = 0.7 V (SI) and different temperatures.

As shown in Fig. 8, the measured data at VGS = 0.35 V are further analyzed to explain the noise mechanism of 40-nm n-MOSFFET in MI region. Obviously, the device noise mechanism in the saturation region is almost entirely determined by intrinsic drain current noise and is near to the full shot noise as expected in Refs. [9] and [13]. As the predictions in the column of VGS = 0.35 V in Table 2, the thermal noise contribution of Rg is greatly reduced in the MI region due to the reduction of gm, and plays a weak role only in the deep triode region. Moreover, because the conduction characteristic of channel is still good, the thermal noise contribution of Rb is very small.

Fig. 8. (color online) Plots of measured and calculated Sid against IDS for 40-nm n-MOSFET at VGS = 0.35 V (MI) and different temperatures.

Also as shown in Fig. 9, the thermal noise characteristics in the WI region are verified by noise measurements at VGS = 0.18 V. The noise behaviors can be determined by further comparing the noise data between 300 K and 77 K at 10 GHz. It is worth emphasizing that the thermal noise behavior of 40-nm n-MOSFET under low voltage weak interaction is very obvious. As the predictions in the column of VGS = 0.18 V in Table 2, the thermal noise caused by the substrate coupling (Cdb, Rb) is higher than intrinsic shot noise and thermal noise of Rg, and becomes the main RF noise source in the WI region. The reason is that gm is very small under the condition of low bias voltage in WI region, but Rb is relatively high. In addition, the experimental results in Fig. 9 at 30 GHz and 60 GHz show that the substrate coupling noise is strongly frequency-dependent in the WI region, which makes substrate coupling noise become the focus of low-voltage applications in CMOS technology, especially in millimeter wave band.

Fig. 9. (color online) Plots of measured and calculated Sid against IDS for 40-nm n-MOSFET at VGS = 0.18 V (WI) and different temperatures.
4. Conclusions

The RF physical behaviors of drain current noise of 40-nm n-MOSFET are distinguished by noise measurement and analysis over the extended ranges of bias voltage and temperature. The proposed model here is very attractive and promising for the simulation design of novel RF integrated circuit due to its model accuracy especially in the WI region. The noise modeling and measurement results strongly indicate that the RF noise mechanism of 40-nm n-MOSFET changes from intrinsic suppressed shot noise to thermal noise under the condition of low-voltage weak interaction.

Reference
[1] Navid R Jungemann C Lee T H Dutton R W 2007 J. Appl. Phys. 101 124501
[2] Wang S C Su p Chen K M Liao K H Chen B Y Huang S Y Hung C C Huang G W 2010 IEEE Trans. Microw. Theory Technol. 58 740
[3] Antonopoulos A Bucher M Papathanasiou K Mavredakis N Makris N Sharma R K Sakalas P Schroter M 2013 IEEE Trans. Electron Dev. 60 3726
[4] Chan L H K Yeo K S Chew K W J Ong S N 2015 IEEE Trans. Microw. Theory Technol. 63 141
[5] Chalkiadaki M A Enz C C 2015 IEEE Trans. Microw. Theory Technol. 63 2173
[6] Jeon J Lee J Kim J Park C H Lee H Oh H Kang H K Park B G Shin H 2009 Symposium on VLSI Technology, Jun, 2009 Kyoto, Japan 48
[7] Mahajan V M Patalay P R Jindal R P Shichijo H Martin S Hou F C Machala C Trombley D E 2012 IEEE Trans. Electron Dev. 59 197
[8] Andersson S Svensson C 2005 Electron. Lett. 41 869
[9] Spathis C Birbas A Georgakopoulou 2015 AIP Adv. 5 087114
[10] Tsididis Y 1999 Operation and Modeling of the MOS Transistor Boston, MA WCB/McGraw-Hill 66
[11] Wang J Wang L Wang D D 2016 Acta Phys. Sin. 65 237102 in Chinese
[12] Ong SN Yeo K S Chew W J 2012 Sliod State Electron. 68 32
[13] Smit G D J Scholten A J Pijper R M T Tiemeijer L F van der Toorn R Klaassen D B M 2014 IEEE Trans. Electron Dev. 61 245
[14] Shi J Xiong Y Z Kang K Nan L Lin F 2009 IEEE Trans. Electron Dev. Lett. 30 185
[15] Fabian Z R Reydezel T T Roberto S M A 2015 IEEE Trans. Microw. Theory Technol. 63 4255
[16] Ytterdal T Cheng Y H Fjeldly T A 2003 Device Modeling for Analog and RF CMOS Circuit Design John Wiley & Sons, Ltd Chapter 3
[17] Himmerlfarb M Belostotski 2016 IEEE Trans. Microw. Theory Technol. 64 258
[18] Wang D D 2017 Equivalent Circuit Modeling of Nanoscale MOSFET in Millimeter-wave Band Dissertation Mianyang Southwest University of Science and Technology in Chinese
[19] Wang J Chen H L Tang G D 2003 Chin. J. Electron. 12 471
[20] Lee C I Lin W C Lin Y T 2015 IEEE Trans. Electron Dev. Lett. 36 291
[21] Chan L H K Yeo K S Chew K W J Ong S N Loo X S Boon C C Do M A 2012 IEEE Trans. Electron Dev. Lett. 33 1117